This invention relates to the fabrication of integrated circuits and, more particularly, to a method for producing a capacitor in an integrated circuit. The method according to the invention is especially suited for making a decoupling capacitor included in an integrated circuit.
The high switching rates used in a modern integrated circuit may cause the supply voltage to degrade at certain points in the circuit and may cause circuit failures. Capacitors may be used to reduce supply voltage variations arising from high switching rates in the supplied circuits. These decoupling capacitors are connected between the supply voltage and ground in parallel with the supplied circuit. This parallel capacitance tends to decouple the voltage supply from disturbances induced by activity in the supplied circuit and allow the voltage supply to remain at the intended level.
In earlier integrated circuits, the decoupling capacitance could be placed off-chip due to the relatively slow cycle times at which the earlier circuits operated. The relatively low frequency response exhibited by these off-chip capacitor structures could still accommodate the relatively slow switching rates of the earlier circuits. In addition, the on-chip circuitry itself provided a large amount of near-by decoupling capacitance. As semiconductor fabrication technologies advance, however, circuit devices such as transistors are packed more and more densely on integrated circuit chips. At the same time, the resulting circuits operate at faster cycle times. At current cycle times on the order of 1 GHz, off-chip capacitance takes many processor cycles to respond. The slow frequency response of off-chip capacitance makes off-chip capacitor arrangements unsuitable for providing the decoupling capacitance necessary to prevent circuit failures in these faster integrated circuit devices. Further, silicon-on-insulator (xe2x80x9cSOIxe2x80x9d) technology allows for still faster cycle times, while further reducing the capacitance of on-chip, non-switching circuitry.
In order to provide sufficient decoupling capacitance at the frequency response necessary in modern higher-frequency circuits, the capacitance must be moved closer to the switching circuitry, onto the integrated circuit chip itself. However, the on-chip capacitance must be provided in an area-efficient manner so as not to take up excessive space on the respective chip. Also, on-chip capacitors should be easy to fabricate along with the active and passive circuit elements which make up the desired integrated circuit.
It is an object of the invention to provide a method of producing a semiconductor capacitor, and particularly a semiconductor capacitor which is readily fabricated on a semiconductor chip with other circuit devices in either bulk or SOI technology. Another object of the invention is to provide a method for improving area efficiency and the frequency response from the semiconductor capacitor.
The capacitor according to the invention is implemented in an integrated circuit chip along with other devices at the device level in the chip structure. xe2x80x9cDevice levelxe2x80x9d in this sense means the level in the integrated circuit at which transistors and other circuit elements are formed. The method of producing the capacitor includes producing an elongated device body formed from a first semiconductor material. Lateral regions preferably formed from a second semiconductor material are produced on both lateral sides of the device body. The method also includes forming a dielectric layer over both lateral regions and the device body, and forming an anode layer over the dielectric layer in an area defined by the device body. The fabrication method also includes covering the entire structure with a suitable insulating material for isolation purposes. Thus, the capacitor according to the invention is produced similar to an insulated gate field effect transistor (xe2x80x9cIGFETxe2x80x9d) with the two lateral regions analogous to the source and drain regions of the transistor structure, and the anode analogous to the gate of the transistor structure.
According to the invention, each lateral region is coupled to ground at a first end of the elongated device body. The anode layer is coupled to the chip supply voltage at a second end of the device body opposite to the first end. With the lateral regions of the structure coupled to ground and the anode coupled to the supply voltage, the capacitor device operates similarly to a IGFET in accumulation mode. Since the lateral regions, analogous to the source and drain of an IGFET, are both coupled to ground, no current flows across the device body. Rather, the device functions as a capacitor between the supply voltage and ground with a positive charge accumulating in the anode material and a negative charge accumulating in the device body material along the dielectric layer. The capacitor structure exhibits a high frequency response due to the location of the structure on-chip and due to the sizing of the device body to maintain a low effective resistance in the device body. Thus, the capacitor structure is capable of effectively decoupling the supply voltage from the effect of high frequency circuits on the chip.
The present capacitor structure may be implemented both in standard CMOS semiconductor technology (commonly referred to as xe2x80x9cbulkxe2x80x9d semiconductor technology), and in SOI technology. Since the capacitor devices are formed at the device level using the same manufacturing process steps with other circuit devices, the present capacitor structure may be fabricated easily along with other devices on-chip to provide effective decoupling capacitance with a high frequency response.
When implemented in bulk, the device body may be constructed in an N-well formed in a P-type material substrate. The device body may comprise a region relatively heavily doped with N-type impurities. Each lateral region may comprise a more heavily doped N-type material. The dielectric layer may comprise a thin layer of silicon dioxide while the anode layer may comprise a suitable metal or preferably polycrystalline silicon.
When implemented in SOI technology the device body is formed above a buried oxide layer and may comprise an N-type semiconductor material. Each lateral region may comprise an N+ material. As in the bulk implementation, the dielectric material may comprise a thin layer of silicon dioxide deposited over both lateral regions and the device body. The anode of either metal or polycrystalline silicon is formed over the dielectric layer and the entire device is isolated further by a suitable insulating material.
In the case of either bulk or SOI implementation, the invention preferably includes forming a first end region from the same semiconductor material as the lateral regions. This first end region extends along a first end of the device body and contacts each lateral region at the first end of the device body. The invention includes coupling the first end region to ground preferably with one or more very low resistance contacts to a wiring layer in the chip structure. The supply voltage connection to the anode layer is also made with one or more very low resistance contacts. Contacts to the anode preferably meet the anode at a second end of the device body and extend upwardly to a wiring layer of the chip structure.
These and other objects, advantages, and features of the invention will be apparent from the following description of the preferred embodiments, considered along with the accompanying drawings.